No activity on the interface is kind of clue. Email Required, but never shown. Rich Maes 6 Similarly, if you may want to bring out your reset to a pin and check it. Post Your Answer Discard By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of service , privacy policy and cookie policy , and that your continued use of the website is subject to these policies.

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Starting the basic checks, Have you simulated it? Make sure you are using the QIP file to synthesize the design.

Stack Overflow works best with JavaScript enabled. Then, using System Console, I am configuring the Triple Speed Ethernet core as described in the core’s user guide link here at section Register Initialization and instruct the packet generator module also using System Console to start and generate Ethernet packets into the TSE core’s transmit Avalon-ST sink interface ports. Power is usually less of problem on devkits if you have already run the demo that came with the kit.

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This doesn’t seem like your issue to me because you say the GMII is flat lined. Alot of times, this goes in the.

Post as a guest Name. It should define a pin for reset, input clock and signal standards.

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By clicking “Post Your Answer”, you acknowledge that you have read our updated terms of serviceprivacy policy and cookie policyand that your continued use of the website is subject to these policies.

Email Required, but never shown. Pins can cause a whole slew of issues if they are not mapped right on this core.

Altera TSE: Change driver name used by Ethtool [Linux 3.15]

By using our site, you acknowledge that you have read and understand our Cookie PolicyPrivacy Policyand our Terms of Service. If you haven’t simulated, you really should. I’ll assume you are leveraging something from Terasic.

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You will still need to add your own PIN constraints, more on that later. Rich Maes 6 It’s not clear to me if you are just simulating or synthesizing. Can any one please, please help me with this? One way altea check, is to route your clocks to spare pins and o-scope them and insure they are what you think they are.

Itamar FPGA 1 1. Similarly, if you may want to bring out your reset to a pin and check it. Sign up using Email and Password.

Linux source code: drivers/net/ethernet/altera/altera_tse_main.c (v) – Bootlin

It will automatically include your auto generated SDC constraints. If it’s not working in SIM, why would it ever work in real life. No activity on the interface is kind of clue.