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Starting the basic checks, Have you simulated it? Make sure you are using the QIP file to synthesize the design.
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This doesn’t seem like your issue to me because you say the GMII is flat lined. Alot of times, this goes in the.
Post as a guest Name. It should define a pin for reset, input clock and signal standards.
Email Required, but never shown. Pins can cause a whole slew of issues if they are not mapped right on this core.
Altera TSE: Change driver name used by Ethtool [Linux 3.15]
You will still need to add your own PIN constraints, more on that later. Rich Maes 6 It’s not clear to me if you are just simulating or synthesizing. Can any one please, please help me with this? One way altea check, is to route your clocks to spare pins and o-scope them and insure they are what you think they are.
Itamar FPGA 1 1. Similarly, if you may want to bring out your reset to a pin and check it. Sign up using Email and Password.
Linux source code: drivers/net/ethernet/altera/altera_tse_main.c (v) – Bootlin
It will automatically include your auto generated SDC constraints. If it’s not working in SIM, why would it ever work in real life. No activity on the interface is kind of clue.